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19-4663; Rev 0; 5/09
Dual PWM Step-Down Converter in a 2mm x 2mm Package for WCDMA PA and RF Power
General Description
The MAX8896 dual step-down converter is optimized for powering the power amplifier (PA) and RF transceiver in WCDMA handsets. This device integrates a highefficiency PWM step-down converter (OUT1) for medium and low-power transmission, and a 140m (typ) bypass FET to power the PA directly from the battery during high-power transmission. A second highefficiency PWM step-down converter (OUT2) supplies power directly to a high PSRR, low output noise, 200mA low-dropout linear regulator (LDO) to power the RF transceiver. Fast switching allows the use of small ceramic input and output capacitors while maintaining low ripple voltage. The feedback network is integrated reducing external component count and total solution size. OUT1 uses an analog input driven by an external DAC to control the output voltage linearly for continuous PA power adjustment. At high duty cycle, OUT1 automatically switches to bypass mode, connecting the input to the output through a low-impedance (140m, typ) MOSFET. OUT2 is a 2MHz fixed-frequency, step-down converter capable of operating at 100% duty cycle. Output accuracy is 2% over load, line, and temperature. The output of OUT2 is preset to 3.1V to provide power to a 200mA, 2.8V LDO designed for low noise (16VRMS, typ), high PSRR (65dB, typ) operation. This configuration provides noise attenuation for the RF transceiver power supply in the 100Hz to 100kHz range. Other features include separate output enables, lowsupply current shutdown, output overcurrent, and overtemperature protection. The MAX8896 is available in a 16-bump, 2mm x 2mm UCSPTM package (0.7mm max height).
Features
o PA Step-Down Converter (OUT1) 7.5s (typ) Settling Time for 0.5V to 1V Output Voltage Change Dynamic Output Voltage Setting from 0.5V to VBATT 140m Bypass PFET and 100% Duty Cycle for Low Dropout 2MHz Switching Frequency Low Output Voltage Ripple 700mA (min) Output Drive Capability 2% Gain Accuracy Tiny External Components o RF Step-Down Converter (OUT2) 2MHz Fixed Switching Frequency 94% Peak Efficiency 100% Duty Cycle 2% Output Accuracy Over Load, Line, and Temperature 200mA (min) Output Drive Capability Tiny External Components o Low-Noise LDO Guaranteed 200mA Output High 65dB (typ) PSRR Fixed Output Voltage Low Noise (16VRMS, typ) o Simple Logic ON/OFF Controls o Low 0.1A Shutdown Current o 2.7V to 5.5V Supply Voltage Range o Thermal Shutdown o 2mm x 2mm UCSP Package (4 x 4 Grid)
MAX8896
Applications
WCDMA/NCDMA Cellular Handsets Smartphones
PART MAX8896EREE+T
Ordering Information
PIN-PACKAGE 16 UCSP (0.5mm pitch) LDO VOLTAGE 2.80V
Note: Device operates over the -40C to +85C temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel.
UCSP is a trademark of Maxim Integrated Products, Inc.
Pin Configurations appear at end of data sheet.
1
________________________________________________________________ Maxim Integrated Products
For information on other Maxim products, visit Maxim's website at www.maxim-ic.com.
Dual PWM Step-Down Converter in a 2mm x 2mm Package for WCDMA PA and RF Power MAX8896
ABSOLUTE MAXIMUM RATINGS
VCC, IN1, IN2, PAEN, RFEN1, RFEN2, REFIN, OUT2, REFBP to AGND .........................-0.3V to +6.0V PAOUT to AGND........................................-0.3V to (VIN1 + 0.3V) LDO to AGND .........................................-0.3V to (VOUT2 + 0.3V) IN1, IN2 to VCC ......................................................-0.3V to +0.3V IN1 to IN2 ..............................................................-0.3V to +0.3V PGND1, PGND2 to AGND.....................................-0.3V to +0.3V LX1 Current .......................................................................1ARMS LX2 Current .......................................................................1ARMS IN1 and PAOUT Current....................................................1ARMS PAOUT, OUT2, LDO Short Circuit to PGND1, PGND2 ....................................................................Continuous Continuous Power Dissipation (TA = +70C) 16-Bump UCSP (derate 12.5mW/C above +70C) ............1W Junction-to-Ambient Thermal Resistance (JA) (Note 1)...96C/W Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Bump Temperature (soldering, reflow) ...........................+260C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = VIN1 = VIN2 = VPAEN = VRFEN1 = VRFEN2 = 3.6V, VREFIN = 0.72V, TA = -40C to +85C, typical values are at TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER INPUT SUPPLY Input Voltage Input Undervoltage Threshold Shutdown Supply Current LOGIC CONTROL PAEN, RFEN1, RFEN2 Logic Input High Voltage PAEN, RFEN1, RFEN2 Logic Input Low Voltage PAEN, RFEN1, RFEN2 Internal Pulldown Resistor PAEN, RFEN1, RFEN2 Logic Input Current REFBP REFBP Output Voltage THERMAL PROTECTION Thermal Shutdown OUT1 Quiescent Supply Current On-Resistance Load Regulation LX1 Leakage Current VRFEN1 = VRFEN2 = 0V, IPA = 0A, no switching p-channel MOSFET switch, ILX1 = -200mA n-channel MOSFET rectifier, ILX1 = 500mA RL is the inductor resistance VIN1 = 5.5V, VLX1 = 0V TA = +25C TA = +85C 155 0.16 0.17 RL/2 0.1 1 5 0.40 0.40 A V/A A TA rising, 20C typical hysteresis +160 C 0A IREFBP 1A 1.237 1.250 1.263 V VIL = 0 TA = +25C TA = +85C 2.7V VCC 5.5V 2.7V VCC 5.5V 400 800 0.01 0.1 1.3 0.4 1600 1 V V k A VCC, VIN1, VIN2 VCC rising, 180mV typical hysteresis VPAEN = VRFEN1 = VRFEN2 = 0 TA = +25C TA = +85C 2.7 2.52 2.63 0.1 0.1 5.5 2.70 4 V V A CONDITIONS MIN TYP MAX UNITS
2
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Dual PWM Step-Down Converter in a 2mm x 2mm Package for WCDMA PA and RF Power
ELECTRICAL CHARACTERISTICS (continued)
(VCC = VIN1 = VIN2 = VPAEN = VRFEN1 = VRFEN2 = 3.6V, VREFIN = 0.72V, TA = -40C to +85C, typical values are at TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER Peak Current Limit (p-Channel MOSFET) Valley Current Limit (n-Channel MOSFET) Minimum On-Time Minimum Off-Time Power-Up Delay OUT1 REFIN Common-Mode Range REFIN-to-PAOUT Gain Input Resistance BYPASS Bypass Mode Threshold On-Resistance Bypass Current Limit Step-Down Current Limit in Bypass Total Bypass Current Limit Bypass Off-Leakage Current OUT2 Output Voltage OUT2 Leakage Current No-Load Supply Current On-Resistance p-Channel Current-Limit Threshold n-Channel Negative Current Limit Maximum Duty Cycle Minimum Duty Cycle PWM Frequency Power-Up Delay From VRFEN1 or VRFEN2 rising to VLX2 rising 1.8 IOUT2 = 0 to 150mA, VIN2 = VCC = 3.2V to 4.5V VRFEN1 = VRFEN2 = 0 TA = +25C TA = +85C 3.038 3.1 0.01 0.1 2.5 300 300 400 450 400 100 16.5 2.0 35 2.2 75 500 3.162 5 V A mA m m mA mA % % MHz s VPAOUT = VLX1 = 1.5V VCC = VIN1 = 5.5V, VPAOUT = 0V TA = +25C TA = +85C VREFIN falling, 150mV hysteresis p-channel MOSFET IOUT = -90mA VPAOUT = 1.5V TA = +25C TA = +85C 700 1200 1900 0.396 xVCC 0.14 0.3 1000 1450 2450 0.01 1 1400 1700 3100 5 V mA mA mA A VREFIN = 0.32V or 1.32V, ILX1 = 0A 0.2 2.45 2.5 320 1.7 2.55 k V From VPAEN rising to VLX1 rising CONDITIONS MIN 1200 1100 TYP 1450 1350 70 50 50 75 MAX 1700 1600 UNITS mA mA ns ns s
MAX8896
VPAEN = 0V, IOUT2 = 0A, switching p-channel MOSFET switch, ILX2 = -40mA n-channel MOSFET rectifier, ILX2 = 40mA
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Dual PWM Step-Down Converter in a 2mm x 2mm Package for WCDMA PA and RF Power MAX8896
ELECTRICAL CHARACTERISTICS (continued)
(VCC = VIN1 = VIN2 = VPAEN = VRFEN1 = VRFEN2 = 3.6V, VREFIN = 0.72V, TA = -40C to +85C, typical values are at TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER LDO Output Voltage, VLDO Current Limit Dropout Voltage Line Regulation Load Regulation Power-Supply Rejection VLDO/VOUT2 Output Noise Minimum Output Capacitance for Stable Operation Output Leakage Current Power-Up Delay VOUT2 = 3.1V, ILDO = 1mA to 200mA VOUT2 = 3.1V, VLDO = 0V VOUT2 = 3.1V, ILDO = 100mA VOUT2 stepped from 3.5V to 5.5V, ILDO = 100mA VOUT2 = 3.1V, ILDO stepped from 50A to 200mA VOUT2 = 3.1V, 10Hz to 10kHz, CLDO = 1F, ILDO = 100mA 100Hz to 100kHz, CLDO = 1F, ILDO = 100mA 0 < ILDO < 200mA VOUT2 = 3.1V, VRFEN1 = VRFEN2 = 0V From VRFEN1 or VRFEN2 rising to VLDO rising 2.744 250 2.800 420 70 2.4 25 65 16 1 25 50 2.856 750 V mA mV mV mV dB VRMS F nA s CONDITIONS MIN TYP MAX UNITS
Note 2: All devices are 100% production tested at TA = +25C. Limits over the operating temperature range are guaranteed by design.
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Dual PWM Step-Down Converter in a 2mm x 2mm Package for WCDMA PA and RF Power
Typical Operating Characteristics
(VCC = VIN1 = VIN2 = 3.6V, VREFIN = 0.72V, circuit of Figure 3, TA = +25C, unless otherwise noted.)
OUT1 PA STEP-DOWN CONVERTER EFFICIENCY vs. LOAD CURRENT VPA = 3.18V
MAX8896 toc03 MAX8896 oc02
MAX8896
OUT1 PA BYPASS MODE DROPOUT VOLTAGE vs. PA LOAD CURRENT
MAX8896 toc01
OUT1 PA STEP-DOWN CONVERTER EFFICIENCY vs. OUTPUT VOLTAGE
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 VIN1 = 3.2V VIN1 = 4.2V VIN1 = 3.6V EFFICIENCY (%) RPA = 7.5 70 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 100 90 85 80 75 BYPASS MODE 100 95
80 70 DROPOUT VOLTAGE (mV) 60 50 40 30 20 10 0 0 100 200 300 400 500 600 VIN1 = 4.2V VIN1 = 3.2V VIN1 = 3.6V
10 0 700 LOAD CURRENT (mA)
200
300
400
500
600
700
OUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
OUT1 PA STEP-DOWN CONVERTER EFFICIENCY vs. LOAD CURRENT VPA = 2.58V
MAX8896 toc04
OUT1 PA STEP-DOWN CONVERTER EFFICIENCY vs. LOAD CURRENT VPA = 1.58V
MAX8896 toc05
OUT1 PA STEP-DOWN CONVERTER EFFICIENCY vs. LOAD CURRENT VPA = 1.18V
MAX8896 toc06
100 95 EFFICIENCY (%) 90 85 80 75 70 50 150 250 350 450 550
100 95 EFFICIENCY (%) 90 85 80 75 70
100 95 EFFICIENCY (%) 90 85 80 75 70
650
50
150
250
350
450
50
150 LOAD CURRENT (mA)
250
LOAD CURRENT (mA)
LOAD CURRENT (mA)
MAX8896 toc07
MAX8896 toc08
95 90 EFFICIENCY (%) 85 80 75 70 65 60 25 75 125 175
95 90 EFFICIENCY (%) 85 80 75 70 65 60
1.88 1.86 OUTPUT VOLTAGE (V) 1.84 1.82 1.80 1.78 1.76 1.74 1.72 1.70
RL = 0.09
225
25
75
125
175
225
0
100
200
300
400
500
600
700
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
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MAX8896 toc09
100
OUT1 PA STEP-DOWN CONVERTER EFFICIENCY vs. LOAD CURRENT VPA = 0.77V
100
OUT1 PA STEP-DOWN CONVERTER EFFICIENCY vs. LOAD CURRENT VPA = 0.56V
OUT1 PA STEP-DOWN CONVERTER OUTPUT VOLTAGE vs. LOAD CURRENT
1.90
5
Dual PWM Step-Down Converter in a 2mm x 2mm Package for WCDMA PA and RF Power MAX8896
Typical Operating Characteristics (continued)
(VCC = VIN1 = VIN2 = 3.6V, VREFIN = 0.72V, circuit of Figure 3, TA = +25C, unless otherwise noted.)
OUT1 PA STEP-DOWN CONVERTER OUTPUT VOLTAGE vs. REFIN VOLTAGE
MAX8896 toc10
OUTPUT VOLTAGE ERROR vs. LOAD CURRENT
3 OUTPUT VOLTAGE ERROR (%) 2 1 0 -1 -2 -3 -4 VOUT = 3.18V VOUT = 0.56V
MAX8896 toc11 MAX8896 toc13
4.0 3.5 OUTPUT VOLTAGE (V) 3.0 2.5 2.0 1.5 1.0 0.5
4
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 REFIN VOLTAGE (V)
0
100 200 300 400 500 600 700 800 LOAD CURRENT (mA)
OUT1 LIGHT-LOAD SWITCHING WAVEFORMS
5mA LOAD
OUT1 HEAVY-LOAD SWITCHING WAVEFORMS
500mA LOAD 200mA/div ILX1 200mA/div
MAX8896 toc12
IL1 VPA 20mV/div (AC-COUPLED) VPA 20mV/div (AC-COUPLED)
VLX1
2V/div
VLX1
2V/div
200ns/div
200ns/div
OUT1 STARTUP AND SHUTDOWN
MAX8896 toc14
VPAEN
5V/div
1V/div VPA
IL1 500mA/div
20s/div
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Dual PWM Step-Down Converter in a 2mm x 2mm Package for WCDMA PA and RF Power
Typical Operating Characteristics (continued)
(VCC = VIN1 = VIN2 = 3.6V, VREFIN = 0.72V, circuit of Figure 3, TA = +25C, unless otherwise noted.)
MAX8896
OUT1 LINE TRANSIENT RESPONSE
MAX8896 toc15
OUT1 LOAD TRANSIENT RESPONSE
MAX8896 toc16
4.0V VIN 500mV/div 3.5V IOUT 10mV/div (AC-COUPLED) 200mA/div 0mA VPA 100mV/div (AC-COUPLED) 500mA
VPA
IL1 50mA LOAD 20s/div
200mA/div
10s/div
OUT1 REFIN TRANSIENT RESPONSE
MAX8896 toc17
OUT1 REFIN TRANSIENT RESPONSE WITH BYPASS EVENT
MAX8896 toc18
VREFIN 0.2V VPA
0.72V 1.8V 500mV/div
1.8V VREFIN 0.6V 3.3V 1V/div 500mV/div VPA 1V/div
IL1
0.5V IL1 1A/div 2.5 LOAD 10s/div 10s/div 1A/div
OUT2 EFFICIENCY vs. LOAD CURRENT
MAX8896 toc19
OUT2 VOLTAGE vs. LOAD CURRENT
3.11 OUTPUT VOLTAGE (V) 3.10 3.09 3.08 3.07 3.06 3.05 3.04 VCC = 3.2V* *OUT2 IN DROPOUT VCC = 3.6V VCC = 4.2V
MAX8896 toc20
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 50 100 150 VCC = 3.2V VCC = 3.6V VCC = 4.2V
3.12
200
0
50
100
150
200
LOAD CURRENT (mA)
LOAD CURRENT (mA)
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Dual PWM Step-Down Converter in a 2mm x 2mm Package for WCDMA PA and RF Power MAX8896
Typical Operating Characteristics (continued)
(VCC = VIN1 = VIN2 = 3.6V, VREFIN = 0.72V, circuit of Figure 3, TA = +25C, unless otherwise noted.)
OUT2 LIGHT-LOAD SWITCHING WAVEFORMS
MAX8896 toc21
OUT2 HEAVY-LOAD SWITCHING WAVEFORMS
MAX8896 toc22
VLX2
5V/div
VLX2
5V/div
VOUT2
10mV/div (AC-COUPLED)
VOUT2 IL2
10mV/div (AC-COUPLED) 200mA/div
IL2 20mA LOAD 200ns/div
200mA/div
200mA LOAD 200ns/div
OUT2 STARTUP WAVEFORM
MAX8896 toc23
OUT2 LINE TRANSIENT RESPONSE
MAX8896 toc24
2V/div VOUT2
4.0V VIN 3.5V 500mV/div
IL2 200mA/div VRFEN_ 5V/div
VOUT2
50mV/div (AC-COUPLED)
IL2 20mA LOAD
200mA/div
10s/div
20s/div
OUT2 LOAD TRANSIENT RESPONSE
MAX8896 toc25
OUT2 DROPOUT VOLTAGE vs. LOAD CURRENT
0.18 0.16 DROPOUT VOLTAGE (V) VIN = 2.7V RL = 0.3
MAX8896 toc26
0.20
150mA IOUT2 100mA/div 0mA 100mV/div (AC-COUPLED)
0.14 0.12 0.10 0.08 0.06 0.04 0.02 0
VOUT2
10s/div
0
50
100
150
200
LOAD CURRENT (mA)
8
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Dual PWM Step-Down Converter in a 2mm x 2mm Package for WCDMA PA and RF Power
Typical Operating Characteristics (continued)
(VCC = VIN1 = VIN2 = 3.6V, VREFIN = 0.72V, circuit of Figure 3, TA = +25C, unless otherwise noted.)
MAX8896
LDO OUTPUT VOLTAGE vs. LOAD CURRENT
MAX8896 toc27
LDO DROPOUT VOLTAGE vs. LOAD CURRENT
0.18 0.16 DROPOUT VOLTAGE (V) 0.14 0.12 0.10 0.08 0.06 0.04 0.02 VOUT2 = 2.7V
MAX8896 toc28
2.82 2.81 OUTPUT VOLTAGE (V) 2.80 2.79 2.78 2.77 2.76 0 50 100 150 200
0.20
0 250 0 50 100 150 200 LOAD CURRENT (mA) LOAD CURRENT (mA)
LDO LOAD TRANSIENT RESPONSE
MAX8896 toc29
LDO STARTUP WAVEFORM
MAX8896 toc30
80mA ILDO 50mA/div 10mA VOUT2 VLDO 20mV/div (AC-COUPLED) VLDO VRFEN1
2V/div
2V/div
2V/div
200mA LOAD ON LDO 4s/div 400s/div
LDO OUTPUT NOISE (OUT1, OUT2, AND LDO ENABLED)
MAX8896 toc31
LDO OUTPUT-NOISE SPECTRAL DENSITY vs. FREQUENCY (OUT1, OUT2, AND LDO ENABLED)
MAX8896 toc32
10E+3
NOISE DENSITY (nV/Hz)
1E+3
VLDO
10V/div
100E+0
10E+0
30mA LOAD 1E+0 400s/div 0.01 0.1 1 10 100 1,000 10,000 FREQUENCY (kHz)
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Dual PWM Step-Down Converter in a 2mm x 2mm Package for WCDMA PA and RF Power MAX8896
Pin Description
PIN A1 A2 A3 A4 B1 B2 NAME REFBP AGND REFIN PGND1 LDO PAEN FUNCTION Reference Noise Bypass. Bypass REFBP to AGND with a 0.033F ceramic capacitor to reduce noise on the LDO output. REFBP is internally pulled down through a 1k resistor during shutdown. Low-Noise Analog Ground. Connect AGND to the ground plane at a single point away from high switching currents. See the PCB Layout section. DAC-Controlled Input. The output of the PA step-down converter is regulated to 2.5 x VREFIN. When VREFIN reaches 0.396 x VCC, bypass mode is enabled. Power Ground for OUT1. Connect PGND1 to the ground plane near the input and output capacitor grounds. See the PCB Layout section. 200mA LDO Regulator Output. Bypass LDO with a 1F ceramic capacitor as close as possible to LDO and ground. Leave LDO unconnected if not used. OUT1 Enable Input. Connect PAEN to IN1 or logic-high for normal operation. Connect to ground or logic-low to shut down OUT1. Internally connected to ground through an 800k resistor. OUT2 and LDO Enable Input. Connect RFEN1 or RFEN2 to IN2 or logic-high for normal operation. Connect RFEN1 and RFEN2 to ground or logic-low to shut down OUT2 and the LDO. Internally connected to ground through an 800k resistor. Inductor Connection. Connect an inductor from LX1 to the output of OUT1. Output of OUT2. OUT2 is also the supply voltage input for the LDO. Bypass OUT2 with a 2.2F ceramic capacitor as close as possible to OUT2 and PGND2. OUT2 and LDO Enable Input. Connect RFEN1 or RFEN2 to IN2 or logic-high for normal operation. Connect RFEN1 and RFEN2 to ground or logic-low to shut down OUT2 and the LDO. Internally connected to ground through an 800k resistor. Supply Voltage Input for Internal Reference and Control Circuitry. Connect VCC to a battery or supply voltage from 2.7V to 5.5V. Bypass VCC with a 0.1F ceramic capacitor as close as possible to VCC and AGND. Connect VCC, IN1, and IN2 to the same source. Supply Voltage Input for OUT1. Connect IN1 to a battery or supply voltage from 2.7V to 5.5V. Bypass IN1 with a 4.7F ceramic capacitor as close as possible to IN1 and PGND1. Connect IN1, VCC, and IN2 to the same source. Power Ground for OUT2. Connect PGND2 to the ground plane near the input and output capacitor grounds. See the PCB Layout section. Inductor Connection. Connect an inductor from LX2 to the output of OUT2. Supply Voltage Input for OUT2. Connect IN2 to a battery or supply voltage from 2.7V to 5.5V. Bypass IN2 with a 2.2F ceramic capacitor as close as possible to IN2 and PGND2. Connect IN2, VCC, and IN1 to the same source. PA Connection for Bypass Mode. Internally connected to IN1 using the internal bypass MOSFET during bypass mode. PAOUT is internally connected to the feedback network for OUT1. Bypass PAOUT with a 4.7F ceramic capacitor as close as possible to PAOUT and PGND1.
B3 B4 C1
RFEN2 LX1 OUT2
C2
RFEN1
C3
VCC
C4
IN1
D1 D2 D3
PGND2 LX2 IN2
D4
PAOUT
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Dual PWM Step-Down Converter in a 2mm x 2mm Package for WCDMA PA and RF Power MAX8896
IN1 R4 R5
BYPASS FET
PA OUT
C1 VCC AGND R7 REFIN R6 C2 EN OUT1 EN OUT1 PWM LOGIC BIAS PWM ERROR COMPARATOR CURRENT-LIMIT CONTROL
R3
LX1
PGND1 STEP DOWN CURRENT LIMIT
R2 VCC
R1 BANDGAP OUT2 LDO CURRENT LIMIT ERROR AMP R9 LDO
REFBP
1.25V REFERENCE BANDGAP
OUT1 EN
PAEN RFEN1 RFEN2
CONTROL LOGIC
R7
IN2
EN
OUT2 PWM LOGIC
LX2
BANDGAP FB NETWORK/ COMPENSATION
PGND2 OUT2
Figure 1. Block Diagram
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11
Dual PWM Step-Down Converter in a 2mm x 2mm Package for WCDMA PA and RF Power MAX8896
Detailed Description
The MAX8896 dual step-down converter is optimized for powering the power amplifier (PA) and RF transceiver in WCDMA handsets. This device integrates a highefficiency PWM step-down converter (OUT1) for medium and low-power transmission, and a 140m (typ) bypass FET to power the PA directly from the battery during high power transmission. A second highefficiency PWM step-down converter (OUT2) supplies power directly to a high PSRR, low-output noise, 200mA low-dropout linear regulator (LDO) to power the RF transceiver.
Automatic Bypass Mode During high-power transmission, the bypass mode connects IN1 directly to PAOUT with the internal 140m (typ) bypass FET, while the step-down converter is forced into 100% duty-cycle operation. The low onresistance in this mode provides low dropout, long battery life, and high output current capability. OUT1 enters bypass mode automatically when V REFIN > 0.396 x VCC (see Figure 2). Current-limit circuitry continuously limits current through the bypass FET to 1000mA (typ). The bypass FET opens up if the voltage at PAOUT drops below 1.25V (typ) in current limit.
OUT1 Step-Down Converter
A hysteretic PWM control scheme ensures high efficiency, fast switching, fast transient response, low output ripple, and physically tiny external components. The control scheme is simple: when the output voltage is below the regulation threshold, the error comparator begins a switching cycle by turning on the high-side switch. This high-side switch remains on until the minimum on-time expires and output voltage is within regulation, or the inductor current is above the current-limit threshold. Once off, the high-side switch remains off until the minimum off-time expires and the output voltage falls again below the regulation threshold. During the off period, the low-side synchronous rectifier turns on and remains on until the high-side switch turns on again. The internal synchronous rectifier eliminates the need for an external Schottky diode.
OUT2 Step-Down Converter
OUT2 is a high-efficiency, 2MHz current-mode stepdown DC-DC converter that outputs 200mA with efficiency up to 94%. The output voltage of the MAX8896 is a fixed 3.1V for powering the LDO. RFEN1 and RFEN2 are dedicated enable inputs for OUT2. Drive RFEN1 or RFEN2 high to enable OUT2, or drive RFEN1 and RFEN2 low to disable OUT2. RFEN1 and RFEN2 have hysteresis so that an RC may be used to implement manual sequencing with respect to other inputs. OUT2 operates with a constant 2MHz switching frequency regardless of output load. The MAX8896 regulates the output voltage by modulating the switching duty cycle. An internal n-channel synchronous rectifier eliminates the need for an external Schottky diode and improves efficiency. The synchronous rectifier turns on during the second half of each switching cycle (offtime). During this time, the voltage across the inductor is reversed, and the inductor current ramps down. The synchronous rectifier turns off at the end of the switching cycle.
Voltage-Positioning Load Regulation The MAX8896 step-down converter utilizes a unique feedback network. By taking DC feedback from the LX node through R1 of Figure 1, the usual phase lag due to the output capacitor is removed, making the loop exceedingly stable and allowing the use of very small ceramic output capacitors. To improve the load regulation, resistor R3 is included in the feedback. This configuration yields load regulation equal to half the inductor's series resistance multiplied by the load current. This voltage-positioning load regulation greatly reduces overshoot during load transients or when changing the output voltage from one level to another. However, when calculating the required REFIN voltage, the load regulation should be considered. Because inductor resistance is typically well specified and the typical PA is a resistive load, the VREFIN to VOUT1 gain is slightly less than 2.5V/V. The output voltage is approximately:
1 VOUT1 = 2.5 x VREFIN - x RL x ILOAD 2
6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 5
2.5
VCC AND PAOUT VOLTAGE (V)
2.0 REFIN VOLTAGE (V)
1.5
1.0
VCC VOLTAGE PAOUT REFIN 10 15 20 25 30 35 40 45 50 TIME (ms)
0.5
0
Figure 2. Automatic Bypass
12
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Dual PWM Step-Down Converter in a 2mm x 2mm Package for WCDMA PA and RF Power
The OUT2 step-down DC-DC converter operates with 100% duty cycle when the supply voltage approaches the output voltage. This allows this converter to maintain regulation until the input voltage falls below the desired output voltage plus the dropout voltage specification of the converter. During 100% duty cycle operation, the high-side p-channel MOSFET turns on constantly, connecting the input to the output through the inductor. The dropout voltage (VDO) is calculated as follows: VDO = ILOAD x (RP + RL) where: RP = internal p-channel MOSFET switch on-resistance (see Electrical Characteristics) RL = external inductor DC resistance
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation in the MAX8896. If the junction temperature exceeds +160C, the MAX8896 turn off, allowing the IC to cool. The IC turns on and begins soft-start after the junction temperature cools by 20C. This results in a pulsed output during continuous thermal-overload conditions.
MAX8896
Applications Information
Inductor Selection
OUT1 operates with a switching frequency of 2MHz and utilizes a 2.2H to 4.7H inductor. OUT2 operates with a switching frequency of 2MHz and utilizes a 2.2H inductor. This operating frequency allows the use of physically small inductors while maintaining high efficiency. The OUT1 inductor's DC current rating only needs to match the maximum load of the application because OUT1 features zero current overshoot during startup and load transients. For optimum transient response and high efficiency, choose an inductor with DC series resistance in the 50m to 150m range. See Table 1 for suggested inductors and manufacturers. Using a larger inductance value reduces the ripple current, therefore providing higher efficiency at light load.
LDO
The LDO provides 200mA at 2.8V and is designed for low noise (16VRMS, typ) and high PSRR (65dB, typ). The LDO is powered from OUT2 (3.1V) and is enabled or disabled at the same time as OUT2 using RFEN1 or RFEN2.
LDO Dropout Voltage The regulator's minimum input/output differential (or dropout voltage) determines the lowest usable supply voltage. In battery-powered systems, this determines the useful end-of-life battery voltage. Because the LDO uses a p-channel MOSFET pass transistor, the dropout voltage is drain-to-source on-resistance (RDS(ON)) multiplied by the load current (see the Typical Operating Characteristics).
Output Capacitor Selection
For OUT1 and OUT2, the output capacitor keeps the output voltage ripple small and ensures regulation loop stability. COUT must have low impedance at the switching frequency. Ceramic capacitors with X5R or X7R temperature characteristics are highly recommended due to their small size, low ESR, and small temperature coefficients. A 4.7F capacitor is recommended for COUT1 and 2.2F is recommended for COUT2. For optimum load-transient performance and very low output ripple, the output capacitor value can be increased. For the LDO, the minimum output capacitance required is dependent on the load currents. For loads lighter than 10mA, it is sufficient to use a 0.1F capacitor for stable operation over the full temperature range. With rated maximum load currents, a minimum of 1F is recommended. Larger value output capacitors further reduce output noise and improve load-transient response, stability, and power-supply rejection. Note that some ceramic dielectrics exhibit large capacitance and ESR variation with temperature and DC bias. Ceramic capacitors with Z5U or Y5V temperature characteristics should be avoided. These regulators are optimized for ceramic capacitors. Tantalum capacitors are not recommended.
Shutdown Mode
Connect PAEN to GND or logic-low to place OUT1 in shutdown mode. In shutdown, the control circuitry, internal switching MOSFET, and synchronous rectifier turn off and LX1 becomes high impedance. Connect PAEN to IN1, VCC, or logic-high for normal operation. Either RFEN1 or RFEN2 enable OUT2 and the LDO. Connect RFEN1 and RFEN2 to GND or logic-low to place OUT2 and the LDO in shutdown mode. In shutdown, the control circuitry, internal switching MOSFET, and synchronous rectifier turn off and LX2 and the LDO output become high impedance. Connect RFEN1 or RFEN2 to IN2, VCC, or logic-high for normal operation. When PAEN, RFEN1, and RFEN2 are all logic-low, the MAX8896 enter a very low power state, where the input current drops to 0.1A (typ).
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13
Dual PWM Step-Down Converter in a 2mm x 2mm Package for WCDMA PA and RF Power MAX8896
2.7V TO 5.5V 0.1F IN1 4.7F VCC
MAX8896
ANALOG CONTROL
REFIN 1000pF
2MHz OUT1
LX1 PAOUT
4.7H*
VPA
PGND1 PAEN RFEN1 CONTROL RFEN2
4.7F
PA ENABLE RF ENABLE 1 RF ENABLE 2
REFBP REF AGND LDO LDO OUT2 IN2 2.2F 2MHz OUT2 2.2H BRL2012T 2R2M LX2 OUT2 PGND2 1F 0.033F VRF (2.8V)
VOUT2 (3.1V) 2.2F
*DE2818C
Figure 3. Typical Applications Circuit
Input Capacitor Selection
The input capacitor (CIN) reduces the current peaks drawn from the battery or input power source and reduces switching noise in the MAX8896. The impedance of CIN at the switching frequency should be kept very low. Ceramic capacitors with X5R or X7R temperature characteristics are highly recommended due to their small size, low ESR, and small temperature coefficients. A 4.7F capacitor is recommended for CIN1 and 2.2F for CIN2. For optimum noise immunity and low input ripple, the input capacitor value can be increased.
Note that some ceramic dielectrics exhibit large capacitance and ESR variation with temperature and DC bias. Ceramic capacitors with Z5U or Y5V temperature characteristics should be avoided.
Thermal Considerations
In most applications, the MAX8896 does not dissipate much heat due to its high efficiency. But in applications where the MAX8896 runs at high ambient temperature with heavy loads, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately +160C, the thermaloverload protection is activated.
14
______________________________________________________________________________________
Dual PWM Step-Down Converter in a 2mm x 2mm Package for WCDMA PA and RF Power
The MAX8896 maximum power dissipation depends on the thermal resistance of the IC package and circuit board, the temperature difference between the die junction and ambient air, and the rate of airflow. The power dissipated in the device is: PD = POUT1 x (1/OUT1 - 1) + POUT2 x (1/OUT2 - 1) + ILDO x (VOUT2 - VLDO) where is the efficiency of the step-down converter and POUT_ is the output power of the step-down converter. The maximum allowed power dissipation is: PMAX = (TJMAX - TA)/JA where (T JMAX - T A ) is the temperature difference between the MAX8896 die junction and the surrounding air, JA is the thermal resistance of the junction through the PCB, copper traces, and other materials to the surrounding air.
PCB Layout
High switching frequencies and relatively large peak currents make the PCB layout a very important part of design. Good design minimizes excessive EMI on the feedback paths and voltage gradients in the ground plane, resulting in a stable and well regulated output. Connect CIN1 close to IN1 and PGND1 and connect CIN2 close to IN2 and PGND2. Connect the inductor and output capacitor as close as possible to the IC and keep their traces short, direct, and wide. Keep noisy traces, such as the LX node, as short as possible. Refer to the MAX8896EVKIT for an example layout.
MAX8896
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15
Dual PWM Step-Down Converter in a 2mm x 2mm Package for WCDMA PA and RF Power MAX8896
Table 1. Suggested Inductors
MANUFACTURER SERIES CB2016T CB2518T Taiyo Yuden BRL2012T CKP2520 2.2 2.2 1.0 1.5 2.2 2.2 1.0 2.2 1.0 1.2 2.2 1.5 2.2 1.5 2.2 4.7 1.2 1.5 2.2 1.5 2.2 3.3 1.0 1.5 2.2 4.7 1.0 2.2 1.0 2.2 0.30 0.09 0.05 0.07 0.08 0.11 0.06 0.10 0.20 0.09 0.15 0.13 0.17 0.10 0.12 72 0.08 0.09 0.12 0.05 0.08 0.10 0.07 0.10 0.13 0.284 0.08 0.12 0.07 0.10 550 1300 1500 1500 1300 1100 1000 790 1170 860 640 1230 1080 1290 1140 950 590 520 440 680 580 450 1600 1400 1100 740 1400 1000 1400 1100 2.0mm x 1.25mm x 1.0mm = 2.5mm3 2.5mm x 2.0mm x 1.0mm = 5mm3 2.5mm x 2.0mm x 1.0mm = 5mm3 2.0mm x 1.6mm x 1.0mm = 3.2mm3 3.2mm x 2.5mm x 1.7mm = 14mm3 3.0mm x 3.0mm x 1.0mm = 9mm3 3.0mm x 3.0mm x 1.2mm = 11mm3 3.6mm x 3.6mm x 1.0mm = 13mm3 3.6mm x 3.6mm x 1.2mm = 16mm3 3.2mm x 3.0mm x 1.8mm = 17.3mm3 3.0mm x 3.0mm x 1.0mm = 9mm3 INDUCTANCE (H) 1.0 2.2 2.2 4.7 ESR () 0.09 0.13 0.09 0.13 CURRENT RATING (mA) 600 510 510 340 DIMENSIONS 2.0mm x 1.6mm x 1.8mm = 5.8mm3 2.5mm x 1.8mm x 2.0mm = 9mm3
MIPF2520 FDK MIPF2016 Murata LQH32C_53 D3010FB D2812C TOKO D310F D312C DE2818C
CDRH2D09 Sumida CDRH2D11
3.2mm x 3.2mm x 1.2mm = 12mm3
LPO3310 Coilcraft XPL2010 ELC3FN Panasonic ELL3GM
3.3mm x 3.3mm x 1.0mm = 11mm3 1.9mm x 2.0mm x 1.0mm = 3.8mm3 3.2mm x 3.2mm x 1.2mm = 12mm3 3.2mm x 3.2mm x 1.5mm = 15mm3
16
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Dual PWM Step-Down Converter in a 2mm x 2mm Package for WCDMA PA and RF Power
Pin Configuration
TOP VIEW (BUMPS ON BOTTOM) MAX8896 1 REFBP A A1 LDO B B1 OUT2 C C1 PGND2 D D1 2 AGND A2 PAEN B2 RFEN1 C2 LX2 D2 3 REFIN A3 RFEN2 B3 VCC C3 IN2 D3 4 PGND1 A4 LX1 B4 IN1 C4 PAOUT D4
Chip Information
PROCESS: BiCMOS
MAX8896
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 16 UCSP PACKAGE CODE R162A2+1 DOCUMENT NO. 21-0226
16-BUMP UCSP
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
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